System clock mode selection.
Controls the master CPU clock frequency and pixel clock, which in turn determines horizontal resolution. Changing the clock triggers a partial hardware reset (VDP1/VDP2/SCSP registers are destroyed).
- Warning
- Changing the clock mode resets VDP1, VDP2, SCSP, and the slave SH2. DRAM content is destroyed. SDRAM and CD block are preserved. See SetClockMode() for details.
- See also
- SetClockMode(), GetClockMode()
| Enumerator |
|---|
| Mode26MHz | 26.0 MHz CPU clock (320/640 pixels per line).
Standard resolution. 320px non-interlaced, 640px interlaced.
|
| Mode28MHz | 28.6 MHz CPU clock (352/704 pixels per line).
High resolution. 352px non-interlaced, 704px interlaced.
|
